- #The signal state solutions generator
- #The signal state solutions series
- #The signal state solutions free
The other way is to generate two equal signal sections (true signal and zeros), then upload them both to the generation and set up a sophisticated scenario to switch sections on the external trigger. But, to be honest, I’d pick that option if I hadn’t came up with a USB-TTL stick idea. The solution is to fill the space afterwards the signal with a lot (A LOT) of zeros, but it’s extremely memory inefficient.
#The signal state solutions generator
Std::chrono is a great tool, it’s really precise, but the problems begin when we’re dealing with the fast signals (up to 1 ms), because TCP/IP is extremely slow for this signal and won’t stop the generator when it’s required. Std :: this_thred :: sleep_for ( std :: chrono :: microseconds ( N )) Pretty obvious solution is to start a generator, wait for the signal to end (because the samples quantity and the sampling frequency are known) and turn the generator (Arbitrary waveform generator if precisely) off. There are some other approaches I’ve tried, but they’re either not working so well or too hard to implement. Of course any additional hardware is a bad decision. The question is how can I get this trigger (preferably within the Visual Studio)? Two hours of searches and testing stuff from our big box of junk with WinAPI and a multimeter gave me a solution: USB-TTL stick! It’s cheap, it interacts with OS like a virtual COM port and it gives great trigger pulses for the generator.
#The signal state solutions free
The signal state may be set to either the free run (infinite number of repeats), or to the single run by a TTL-trigger. Today I’ve found the only flaw in the generator I’m working with: one can’t simply run the signal once without an external trigger. Remote control allows us to set up the test script, launch it to acquire the information and have some time to play ping-pong, go for a coffee break, or write an article about how cool is it to be an engineer nowadays.
#The signal state solutions series
series of tests every one on which requires different signal from the generator. And to test our brand-new algorithm we create the suiting environment: i.e. When this stage is over it’s time to migrate the algorithm to the external hardware. Then the model has to be modified step by step to approximate or even simulate the hardware platform. Models are easy to debug and are very important to estimate the performance and the qualitative characteristics. At first developer should do some theoretical investigation to make a plausible model. Let’s assume that we have a great and bug-free (which isn’t always true) hardware platform, some SoC or an ASIC, and we want to implement a brand-new algorithm.
To explain this idea I have to specify the development cycle of the new equipment.
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